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| publication number s29ws-p_00 revision a amendment 12 issue date january 28, 2008 s29ws-p s29ws-p cover sheet mirrorbit ? flash family s29ws512p, s29ws256p, s29ws128p 512/256/128 mb (32/ 16/8 m x 16 bit) 1.8 v burst simultaneous read/ write mirrorbit flash memory data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office. publication number s29ws-p_00 revision a amendment 12 issue date january 28, 2008 features ? single 1.8 v read/program/erase (1.70?1.95 v) ? 90 nm mirrorbit? technology ? simultaneous read/write operation with zero latency ? random page read access mode of 8 words with 20 ns intra page access time ? 32 word / 64 byte write buffer ? sixteen-bank architecture consisting of 32/16/8 mwords for 512/256/128p, respectively ? four 16 kword sectors at both top and bottom of memory array ? 510/254/126 64kword sectors (ws512/256/128p) ? programmable linear (8/16/32) with or without wrap around and continuous burst read modes ? secured silicon sector region consisting of 128 words each for factory and 128 words for customer ? 20-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? command set compatible with jedec (42.4) standard ? hardware (wp#) protection of top and bottom sectors ? dual boot sector configuration (top and bottom) ? handshaking by monitoring rdy ? offered packages ? ws512p/ws256p/ws128p: 84-ball fbga (11.6 mm x 8 mm) ? low v cc write inhibit ? persistent and password methods of advanced sector protection ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? unlock bypass program command to reduce programming time ? synchronous or asynchronous program operation, independent of burst control register settings ? acc input pin to reduce factory programming time ? support for common flash interface (cfi) general description the spansion s29ws512/256/128p are mirrorbit ? flash products fabricated on 90 nm process technology. these burst mode flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. these products can operate up to 104 mhz and use a single v cc of 1.7 v to 1.95 v that makes them ideal for today?s demanding wireless applications r equiring higher density, better performance and lowered power consumption. performance characteristics s29ws-p mirrorbit ? flash family s29ws512p, s29ws256p, s29ws128p 512/256/128 mb (32/ 16/8 m x 16 bit) 1.8 v burst simultaneous read/ write mirrorbit flash memory data sheet read access times speed option (mhz) 104 max. synch access time (t iacc )103.8 max. synch. burst access, ns (t bacc )7.6 max oe# access time, ns (t oe )7.6 max. asynch. access time, ns (t acc )80 current consumption (typical values) continuous burst read @ 104 mhz 36 ma simultaneous operation 104 mhz 40 ma program 20 ma standby mode 20 a typical program & erase times single word programming 40 s effective write buffer programming (v cc ) per word 9.4 s effective write buffer programming (v acc ) per word 6 s sector erase (16 kword sector) 350 ms sector erase (64 kword sector) 600 ms 4 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. input/output descrip tions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. physical dimensions/connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 special handling instructions for fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 mcp look-ahead connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 synchronous (burst) read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5 synchronous (burst) read mode & configuration regist er . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.6 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.7 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.8 simultaneous read/program or erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.9 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.10 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.11 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.12 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8. advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.2 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3 persistent protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.4 dynamic protection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.5 persistent protection bit lock bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.6 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.7 hardware data protection methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9. power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.3 hardware reset# inpu t operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10. secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.2 customer secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.3 secured silicon sector en try/exit command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.4 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.5 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.6 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.7 power-up/initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 january 28, 2008 s29ws-p_00_a12 s29ws-p 5 data sheet 11.8 clk characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.9 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.10 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12. appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figures figure 4.1 84-ball fine-pitch ball grid array, 512, 256 & 128 mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4.2 vbh084?84-ball fine-pitch ball grid array, 11.6 x 8 mm mcp compatible package. . . . . 13 figure 7.1 synchronous/asynchronous state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7.2 synchronous read flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7.3 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7.4 write buffer programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 7.5 sector erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 7.6 write operation status flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 8.1 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 8.2 ppb program/erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8.3 lock register program algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 11.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 11.3 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 11.4 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 11.5 v cc power-up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 11.6 clk characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 11.7 8-word linear synchronous single data rate burst with wrap around . . . . . . . . . . . . . . . . 71 figure 11.8 8-word linear single data read synchronous burst without wrap around . . . . . . . . . . . . . 71 figure 11.9 asynchronous read mode (avd# toggling - case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 11.10 asynchronous read mode (avd# toggling - case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 11.11 asynchronous read mode (avd# toggling - case 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 11.12 asynchronous read mode (avd# tied to ce#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 11.13 asynchronous page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 11.14 reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 11.15 asynchronous program operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 11.16 synchronous program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 11.17 chip/sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 11.18 accelerated unlock bypass programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 11.19 data# polling timings (during embedded algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 11.20 toggle bit timings (during embedded algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 11.21 synchronous data polling timings/toggle bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 11.22 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 11.23 latency with boundary crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11.24 wait state configuration register setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11.25 back-to-back read/write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 january 28, 2008 s29ws-p_00_a12 s29ws-p 7 data sheet tables table 2.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 6.1 s29ws512p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 6.2 s29ws256p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 6.3 s29ws128p sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7.1 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7.2 page select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 7.3 address latency for 11 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 7.4 address latency for 10 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7.5 address latency for 09 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7.6 address latency for 8 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7.7 address latency for 7 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7.8 address latency for 6 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 7.9 address latency for 5 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 7.10 address latency for 4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 7.11 address latency for 3 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 7.12 address latency for 11 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7.13 address latency for 10 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7.14 address latency for 9 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7.15 address latency for 8 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7.16 address latency for 7 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.17 address latency for 6 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.18 address latency for 5 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.19 address latency for 4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.20 address latency for 3 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.21 address latency for 11 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.22 address latency for 10 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.23 address latency for 9 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.24 address latency for 8 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.25 address latency for 7 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.26 address latency for 6 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.27 address latency for 5 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.28 address latency for 4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 7.29 address latency for 3 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 7.30 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 7.31 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7.32 autoselect addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 7.33 autoselect entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 7.34 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 7.35 single word program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 7.36 write buffer program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 7.37 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 7.38 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 7.39 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 7.40 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 7.41 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 7.42 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 7.43 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 7.44 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 7.45 unlock bypass reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 7.46 dq6 and dq2 indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 7.47 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 7.48 reset (lld function = lld_resetcmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 8.1 sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 8.2 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table 8.3 s29ws512p sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 8.4 s29ws256p sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 8.5 s29ws128p sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 10.1 secured silicon sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 10.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 10.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 10.4 secured silicon sector exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 11.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 11.2 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 11.3 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 11.4 non-continuous burst mode with wrap around burst mode. . . . . . . . . . . . . . . . . . . . . . . . . .70 table 11.5 continuous burst mode with no wrap around burst mo de. . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 11.6 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 11.7 example of programmable wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 12.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table 12.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table 12.3 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 12.4 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 12.5 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 12.6 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 january 28, 2008 s29ws-p_00_a12 s29ws-p 9 data sheet 1. ordering information the ordering part number is formed by a valid combination of the following: 1.1 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading s29 and packing type designator from ordering part number. s29ws 512 p xx ba w 00 0 packing type 0 = tray (standard; see note 1 ) 2 = 7-inch tape and reel 3 = 13-inch tape and reel model number (chip enable options) 00 = default temperature range w = wireless (?25 c to +85 c) package type and material ba = very thin fine-pitch bga, lead (pb)-free compliant package bf = very thin fine-pitch bga, lead (pb)-free package speed option (burst frequency) 0l = 54 mhz 0p = 66 mhz 0s = 80 mhz ab = 104 mhz process technology p = 90 nm mirrorbit ? te c h n o l o gy flash density 512= 512 mb 256= 256 mb 128= 128 mb device family s29ws =1.8 volt-only simultaneous read/write, burst mode flash memory s29ws512p valid combinations (notes 1 , 2 ) model numbers package type (note 2) base ordering part number product status speed option package type, material, & temperature range packing type s29ws512p advance 0l, 0p, 0s, ab baw ( lead (pb)-free compliant), bfw ( lead (pb)-free) 0, 2, 3 (note 1) 00 11.6 mm x 8 mm 84-ball mcp-compatible s29ws256p s29ws128p 11.6 mm x 8 mm 84-ball mcp-compatible 10 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 2. input/output descriptions & logic symbol table identifies the input and output packa ge connections provided on the device. table 2.1 input/output descriptions symbol type description a max ?a0 input address lines (amax = 24 for ws512p 1ce# option, 23 for ws512p 2ce# option, 23 for ws256p, and 22 for ws128p) dq15?dq0 i/o data input/output. ce# input chip enable. asynchronous relative to clk. oe# input output enable. asynchronous relative to clk. we# input write enable. v cc supply device power supply v ccq supply device input/output power supply (must be ramped simultaneously with v cc ) v ss supply ground. nc no connect not connected internally. rdy output ready. indicates when valid burst data is ready to be read. clk input clock input. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode. avd# input address valid. indicates to device that the valid address is present on the address inputs. when low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be latched at the next active clock edge. when high, device ignores address inputs. reset# input hardware reset. low = device resets and returns to reading array data. wp# input write protect. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. acc input acceleration input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. rfu reserved reserved for future use (see mcp look-ahead pinout for use with mcp). january 28, 2008 s29ws-p_00_a12 s29ws-p 11 data sheet 3. block diagrams notes: 1. amax-a0 = a24-a0 for the ws512p, a23-a0 for the ws256p, and a22-a0 for the ws128p. 2. n = 15 for ws512p / ws256p / ws128p. 4. physical dimensions/connection diagrams this section shows the i/o designations and package specifications for the s29ws-p. 4.1 related documents the following documents contain information relating to the s29ws-p devices. click on the title or go to www.spansion.com to download the pdf file, or request a copy from your sales office. ? considerations for x-ray inspection of surface-mounted flash integrated circuits 4.2 special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. v ss v cc bank address reset# acc we# cex# avd# rdy dq15?dq0 wp# s tat e control & command register bank 1 x-decoder y-decoder latches and control logic bank 0 x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank (n-1) y-decoder x-decoder latches and control logic bank (n) y-decoder x-decoder latches and control logic oe# status control amax?a0 amax?a0 amax?a0 amax?a0 bank address bank address bank address v ccq 12 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 4.1 84-ball fine-pitch ball grid array, 512, 256 & 128 mb notes: 1. balls f6 and g8 are rfu on the ws128p. 2. ball g8 is rfu on the ws256p. 3. v cc pins must ramp simultaneously. h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 f-ce# h3 oe# rfu dq0 c2 c3 b2 b3 avd# vss wp# a7 a8 we# acc rfu b4 b5 b6 b7 c8 c9 rfu a11 b8 b9 rfu rfu rfu vcc rfu clk a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 a24 dq6 g6 f6 e6 rfu a20 a23 rfu g4 g5 f4 f5 e4 e5 d5 reset# rfu rdy a18 rfu a17 rfu dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu vcc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 vss a0 l2 l3 rfu dq8 rfu rfu vss dq12 rfu dq14 dq5 rfu dq11 dq2 l4 l5 l6 l7 l8 l9 vccq rfu rfu vcc vss a1 nc a10 nc rfu m10 nc m1 nc h2 c4 d4 d6 reserved fo r future use do not use ground j4 j5 j6 j7 j8 j9 j2 j3 k2 k3 k4 k5 k6 k7 k8 k9 power legend (top view, balls facing down, mcp compatible) january 28, 2008 s29ws-p_00_a12 s29ws-p 13 data sheet figure 4.2 vbh084?84-ball fine-pitch ball grid array, 11.6 x 8 mm mcp compatible package note: bsc is an ansi standard for basic space centering. 4.3 mcp look-ahead connection diagram spansion inc. provides this standard lo ok-ahead connection diagram that supports ? nor flash and sram densities up to 4 gigabits ? nor flash and psram densities up to 4 gigabits ? nor flash and psram and data storage densities up to 4 gigabits the physical package outline may vary between connecti on diagrams and densities. the connection diagram for any mcp, however, is a subset of the pinout. 3339 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 084 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 84 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-a9, b10-l10, depopulated solder balls m2-m9, b1-l1) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark 14 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet in some cases, outri gger balls may exist in locations outside the grid shown. thes e outrigger balls are reserved; do not connect them to any other signal. for further information about the mc p look-ahead pinout, refer to the design-in scalable wireless solutions with spansion products application note (publication number: design_scalable_wireless_an), available on the web or through a spansion sales office. january 28, 2008 s29ws-p_00_a12 s29ws-p 15 data sheet 5. additional resources visit www.spansion.com to obtain the following related documents: application notes ? using the operation status bits in amd devices ? understanding burst mode flash memory devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit ? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions specification bulletins contact your local sales office for details. drivers and software support ? spansion low-level drivers ? true flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad ? schematic symbols technical support contact your local sales office or contact spansion inc. directly for additional technical support: http://www.spansion.com/flash_memor y_products/support/ses/index.html spansion inc. locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited cube-kawasaki 9f/10f, 1-14 nisshin-cho, kawasaki-ku, kawasaki-shi, kanagawa, 210-0024, japan phone: 044-223-1700 (active from nov.28th) http://www.spansion.com 16 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 6. product overview the s29ws-p family consists of 512, 256, and 128 mbi t, 1.8 volts-only, simultaneous read/write burst mode flash device optimized for today?s wireless designs that demand a large storage array, rich functionality, and low power consumption. these devices are organized in 32, 16, or 8 mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. these products also offer single word programming or a 32-word buffer for progr amming with program/erase and suspend functionality. additional features include: ? advanced sector protection methods for protecting sectors as required ? 256 words of secured silicon area for storing cust omer and factory secured information. the secured silicon sector is one time programmable. 6.1 memory map the s29ws512/256/128p mbit devices consist of 16 banks organized as shown in tables 6.1 ? 6.3 . note this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa005?sa033) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 6.1 s29ws512p sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 4 mb 4 32 0 sa000 000000h?003fffh sector starting address ? sector ending address 32 sa001 004000h?007fffh 32 sa002 008000h?00bfffh 32 sa003 00c000h?00ffffh 31 128 sa004 010000h?01ffffh sector starting address ? sector ending address (see note) ? ? ? 128 sa034 1f0000h?1fffffh 4 mb 32 128 1 sa035?sa066 200000h?3fffffh first sector, starting address ? last sector, ending address (see note) 4 mb 32 128 2 sa067?sa098 4 mb 32 128 3 sa099?sa130 ? 4 mb 32 128 4 sa131?sa162 ? 4 mb 32 128 5 sa163?sa194 ? 4 mb 32 128 6 sa195?sa226 ? 4 mb 32 128 7 sa227?sa258 e00000h?ffffffh 4 mb 32 128 8 sa259?sa290 1000000-11fffff 4 mb 32 128 9 sa291?sa322 ? 4 mb 32 128 10 sa323?sa354 ? 4 mb 32 128 11 sa355?sa386 ? 4 mb 32 128 12 sa387?sa418 ? 4 mb 32 128 13 sa419?sa450 ? 4 mb 32 128 14 sa451?sa482 1c00000h-1dfffffh 4 mb 31 128 15 sa483 1e00000h-1e0ffffh sector starting address ? sector ending address (see note) ? sa513 1fe0000h-1feffffh 432 sa514 1ff0000h-1ff3fffh sector starting address ? sector ending address sa515 1ff4000h-1ff7fffh sa516 1ff8000h-1ffbfffh sa517 1ffc000h-1ffffffh january 28, 2008 s29ws-p_00_a12 s29ws-p 17 data sheet note this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa005?sa017) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 6.2 s29ws256p sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 2 mb 432 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 15 128 sa004 to sa018 010000h?01ffffh to 0f0000h?0fffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 2 mb 16 128 1 sa019 to sa034 100000h?10ffffh to 1f0000h?1fffffh 2 mb 16 128 2 sa035 to sa050 200000h?20ffffh to 2f0000h?2fffffh 2 mb 16 128 3 sa051 to sa066 300000h?30ffffh to 3f0000h?3fffffh 2 mb 16 128 4 sa067 to sa082 400000h?40ffffh to 4f0000h?4fffffh 2 mb 16 128 5 sa083 to sa098 500000h?50ffffh to 5f0000h?5fffffh 2 mb 16 128 6 sa099 to sa114 600000h?60ffffh to 6f0000h?6fffffh 2 mb 16 128 7 sa115 to sa130 700000h?70ffffh to 7f0000h?7fffffh 2 mb 16 128 8 sa131 to sa146 800000h?80ffffh to 8f0000h?8fffffh 2 mb 16 128 9 sa147 to sa162 900000h?90ffffh to 9f0000h?9fffffh 2 mb 16 128 10 sa163 to sa178 a00000h?a0ffffh to af0000h?afffffh 2 mb 16 128 11 sa179 to sa194 b00000h?b0ffffh to bf0000h?bfffffh 2 mb 16 128 12 sa195 to sa210 c00000h?c0ffffh to cf0000h?cfffffh 2 mb 16 128 13 sa211 to sa226 d00000h?d0ffffh to df0000h?dfffffh 2 mb 16 128 14 sa227 to sa242 e00000h?e0ffffh to ef0000h?efffffh 2 mb 15 128 15 sa243 to sa257 f00000h?f0ffffh to fe0000h?feffffh 432 sa258 ff0000h?ff3fffh contains four smaller sectors at top of addressable memory. sa259 ff4000h?ff7fffh sa260 ff8000h?ffbfffh sa261 ffc000h?ffffffh 18 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their addre ss ranges that are not explicitly listed (such as sa005?sa009) have sector starting and ending addresses that form the same pattern as al l other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. 7. device operations this section describes the read, pr ogram, erase, simultaneous read/writ e operations, handshaking, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see table 12.1 on page 84 and table 12.2 on page 86 ). the command register itself does not occupy any address able memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as input to the in ternal state machine and the state ma chine outputs dictat e the function of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. table 6.3 s29ws128p sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 1 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. 32 sa001 004000h?007fffh 32 sa002 008000h?00bfffh 32 sa003 00c000h?00ffffh 7 128 sa004 to sa010 010000h?01ffffh to 070000h?07ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 1 mb 8 128 1 sa011 to sa018 080000h?08ffffh to 0f0000h?0fffffh 1 mb 8 128 2 sa019 to sa026 100000h?10ffffh to 170000h?17ffffh 1 mb 8 128 3 sa027 to sa034 180000h?18ffffh to 1f0000h?1fffffh 1 mb 8 128 4 sa035 to sa042 200000h?20ffffh to 270000h?27ffffh 1 mb 8 128 5 sa043 to sa050 280000h?28ffffh to 2f0000h?2fffffh 1 mb 8 128 6 sa051 to sa058 300000h?30ffffh to 370000h?37ffffh 1 mb 8 128 7 sa059 to sa066 380000h?38ffffh to 3f0000h?3fffffh 1 mb 8 128 8 sa067 to sa074 400000h?40ffffh to 470000h?47ffffh 1 mb 8 128 9 sa075 to sa082 480000h?48ffffh to 4f0000h?4fffffh 1 mb 8 128 10 sa083 to sa090 500000h?50ffffh to 570000h?57ffffh 1 mb 8 128 11 sa091 to sa098 580000h?58ffffh to 5f0000h?5fffffh 1 mb 8 128 12 sa099 to sa106 600000h?60ffffh to 670000h?67ffffh 1 mb 8 128 13 sa107 to sa114 680000h?68ffffh to 6f0000h?6fffffh 1 mb 8 128 14 sa115 to sa122 700000h?70ffffh to 770000h?77ffffh 1 mb 7128 15 sa123 to sa129 780000h?78ffffh to 7e0000h?7effffh 4 32 sa130 7f0000h?7f3fffh contains four smaller sectors at top of addressable memory. 32 sa131 7f4000h?7f7fffh 32 sa132 7f8000h?7fbfffh 32 sa133 7fc000h?7fffffh january 28, 2008 s29ws-p_00_a12 s29ws-p 19 data sheet 7.1 device operation table the device must be setup appro priately for each operation. table 7.1 describes the required state of each control pin for any particular operation. legend: l = logic 0, h = logic 1, x = can be either v il or v ih ., = rising edge, = high to low, = toggle. note: address is latched on the rising edge of clock. 7.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are present ed to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. the device defaults to reading array data asynchronously after device power-up or hardware reset. to read data from the memory array, the system must first assert a valid address on a max ?a0, while driving avd# and ce# to v il . we# must remain at v ih . the rising edge of avd# latches the address, preventing changes to the address lines from effecting the address being a ccessed.. data is output on dq15-dq0 pins after the access time (t acc ) has elapsed from the falling edge of avd#, or the last time the address lines changed while avd# was low. table 7.1 device operations operation ce# oe# we# clk avd# amax?a0 dq15?0 rdy reset# asynchronous read - addresses latched ll h x addr in output valid hh asynchronous read avd# steady state ll h x l addr in output valid hh asynchronous write l h x l addr in input valid hh synchronous write lh l addr in i/o h h standby (ce#) h x x x x x high z high z h hardware reset x x x x x x high z high z burst read operations latch starting burst address by clk l x h l addr in output invalid xh advance burst read to next address l l h h x output valid hh terminate current burst read cycle h x h x x x high z high z h terminate current burst read cycle via reset# x x h x x x high z high z l terminate current burst read cycle and start new burst read cycle lx h addr in output invalid xh 20 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 7.3 page mode read the device is capable of fast page m ode read. this mode provides fast (t pac c ) random read access speed for locations within a page. address bits amax?a3 select an 8 word page, and address bits a2?a0 select a specific word within that page. this is an asyn chronous operation with the microprocessor supplying the specific word location. it does not matter if avd# st ays low or toggles. however, the address input must be always valid and stable if avd# is low during the page read. the random or initial page access is t acc or t ce (depending on how the device was accessed) and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pa c c . when ce# is deasserted (=v ih ), the reassertion of ce # for subsequent access has access time of t ce . here again, ce# selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping amax?a3 constant and changing a2?a0 to se lect the specific word within that page. 7.4 synchronous (burst) read operation the device is capable of continuous sequential burst operation and linear bu rst operation of a preset length. when the device first powers up, it is enabled for a synchronous read operations and can be automatically enabled for burst mode. to enter into synchronous m ode, the configuration register will need to be set. prior to entering burst mode, the system should determine how many wait states ar e desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired and how the rdy signal will transition with valid data. the system would then write the configuration register command sequence. once the system has written the set configuration register command sequence, the device is enabled for synchronous reads only. the data is output t iacc after the rising edge of the first clk. subs equent words are output t bacc after the rising edge of each successive clock cycle, which automatically increments the internal address counter. note that data is output only at the rising edge of the clock. rdy indicates the initial latency. 7.4.1 latency tables for variable wait state the following tables show the latency for variab le wait state in a continuous burst operation table 7.2 page select word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1 table 7.3 address latency for 11 wait states word initial wait 0 11 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 1 d1d2d3d4d5d6d7 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 2 d2d3d4d5d6d7 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 3 d3d4d5d6d7 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 4 d4d5d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 5d5d6d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 6d6d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 7d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 2 ws d0 january 28, 2008 s29ws-p_00_a12 s29ws-p 21 data sheet table 7.4 address latency for 10 wait states word initial wait 0 10 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 1 d1d2d3d4d5d6d7 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 2 d2d3d4d5d6d7 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 3 d3d4d5d6d7 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 4 d4d5d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 5d5d6d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 6d6d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 7d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 1 ws d0 table 7.5 address latency for 09 wait states word initial wait 0 9 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 ? d124 d125 d126 d127 d0 1 d1d2d3d4d5d6d7 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 2 d2d3d4d5d6d7 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 3 d3d4d5d6d7 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 4 d4d5d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 5d5d6d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 6d6d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 7d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 ? d124 d125 d126 d127 d0 table 7.6 address latency for 8 wait states word initial wait 0 8 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7 1 ws d8 d9 3 d3d4d5d6d7 1 ws 1 ws d8 d9 4 d4d5d6d7 1 ws 1 ws 1 ws d8 d9 5d5d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 6d6d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 7d7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 table 7.7 address latency for 7 wait states word initial wait 0 7 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3 d4 d5 d6 d7 1 ws d8 d9 d10 4 d4d5d6d7 1 ws 1 ws d8 d9 d10 5d5d6d7 1 ws 1 ws 1 ws d8 d9 d10 6d6d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 7d7 1 ws 1 ws 1 ws 1 ws 1 ws d8 d9 d10 22 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table 7.8 address latency for 6 wait states word initial wait 0 6 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3d4d5d6d7d8d9d10d11 4 d4d5d6d7 1 ws d8 d9 d10 d11 5d5d6d7 1 ws 1 ws d8 d9 d10 d11 6d6d7 1 ws 1 ws 1 ws d8 d9 d10 d11 7d7 1 ws 1 ws 1 ws 1 ws d8 d9 d10 d11 table 7.9 address latency for 5 wait states word initial wait 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3d4d5d6d7d8d9d10d11 4 d4d5d6d7d8d9d10d11d12 5d5d6d7 1 ws d8 d9 d10 d11 d12 6d6d7 1 ws 1 ws d8 d9 d10 d11 d12 7d7 1 ws 1 ws 1 ws d8 d9 d10 d11 d12 table 7.10 address latency for 4 wait states word initial wait 0 4 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3d4d5d6d7d8d9d10d11 4 d4d5d6d7d8d9d10d11d12 5 d5d6d7d8d9d10d11d12d13 6d6d7 1 ws d8 d9 d10 d11 d12 d13 7d7 1 ws 1 ws d8 d9 d10 d11 d12 d13 table 7.11 address latency for 3 wait states word initial wait 0 3 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 d1d2d3d4d5d6d7d8 d9 2 d2d3d4d5d6d7d8d9 d10 3 d3d4d5d6d7d8d9d10d11 4 d4d5d6d7d8d9d10d11d12 5 d5d6d7d8d9d10d11d12d13 6 d6d7d8d9d10d11d12d13d14 7d7 1 ws d8 d9 d10 d11 d12 d13 d14 january 28, 2008 s29ws-p_00_a12 s29ws-p 23 data sheet 7.4.2 latency for boundary cr ossing during first read the following tables show the latency at end of word line for boundary corssing during first read in continuous burst operation table 7.12 address latency for 11 wait states word initial wait 0 11 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 1 d121 d122 d123 d124 d125 d126 d127 1 ws 2 ws d0 2 d122 d123 d124 d125 d126 d127 1 ws 1 ws 2 ws d0 3 d123 d124 d125 d126 d127 1 ws 1 ws 1 ws 2 ws d0 4 d124 d125 d126 d127 1 ws 1 ws 1 ws 1 ws 2 ws d0 5 d125 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws 2 ws d0 6 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 2 ws d0 7 d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 2 ws d0 table 7.13 address latency for 10 wait states word initial wait 0 10 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 1 d121 d122 d123 d124 d125 d126 d127 1 ws 1 ws d0 2 d122 d123 d124 d125 d126 d127 1 ws 1 ws 1 ws d0 3 d123 d124 d125 d126 d127 1 ws 1 ws 1 ws 1 ws d0 4 d124 d125 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws d0 5 d125 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d0 6 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d0 7d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d0 table 7.14 address latency for 9 wait states word initial wait 0 9 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121 d122 d123 d124 d125 d126 d127 1 ws d0 2 d122 d123 d124 d125 d126 d127 1 ws 1 ws d0 3 d123 d124 d125 d126 d127 1 ws 1 ws 1 ws d0 4 d124 d125 d126 d127 1 ws 1 ws 1 ws 1 ws d0 5 d125 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws d0 6 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d0 7 d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d0 table 7.15 address latency for 8 wait states word initial wait 0 8 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121d122d123d124d125d126d127 d0 d1 2 d122d123d124d125d126d127 1 ws d0 d1 3 d123d124d125d126d127 1 ws 1 ws d0 d1 4 d124 d125 d126 d127 1 ws 1 ws 1 ws d0 d1 5 d125 d126 d127 1 ws 1 ws 1 ws 1 ws d0 d1 6 d126 d127 1 ws 1 ws 1 ws 1 ws 1 ws d0 d1 7d127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d0 d1 24 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table 7.16 address latency for 7 wait states word initial wait 0 7 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121 d122 d123 d124 d125 d126 d127 d0 d1 2 d122 d123 d124 d125 d126 d127 d0 d1 d2 3 d123 d124 d125 d126 d127 1 ws d0 d1 d2 4 d124 d125 d126 d127 1 ws 1 ws d0 d1 d2 5 d125 d126 d127 1 ws 1 ws 1 ws d0 d1 d2 6 d126 d127 1 ws 1 ws 1 ws 1 ws d0 d1 d2 7 d127 1 ws 1 ws 1 ws 1 ws 1 ws d0 d1 d2 table 7.17 address latency for 6 wait states word initial wait 0 6 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121 d122 d123 d124 d125 d126 d127 d0 d1 2 d122 d123 d124 d125 d126 d127 d0 d1 d2 3 d123 d124 d125 d126 d127 d0 d1 d2 d3 4 d124 d125 d126 d127 1 ws d0 d1 d2 d3 5 d125 d126 d127 1 ws 1 ws d0 d1 d2 d3 6 d126 d127 1 ws 1 ws 1 ws d0 d1 d2 d3 7 d127 1 ws 1 ws 1 ws 1 ws d0 d1 d2 d3 table 7.18 address latency for 5 wait states word initial wait 0 5 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121 d122 d123 d124 d125 d126 d127 d0 d1 2 d122 d123 d124 d125 d126 d127 d0 d1 d2 3 d123 d124 d125 d126 d127 d0 d1 d2 d3 4 d124 d125 d126 d127 d0 d1 d2 d3 d4 5 d125 d126 d127 1 ws d0 d1 d2 d3 d4 6 d126 d127 1 ws 1 ws d0 d1 d2 d3 d4 7d127 1 ws 1 ws 1 ws d0 d1 d2 d3 d4 table 7.19 address latency for 4 wait states word initial wait 0 4 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121 d122 d123 d124 d125 d126 d127 d0 d1 2 d122 d123 d124 d125 d126 d127 d0 d1 d2 3 d123 d124 d125 d126 d127 d0 d1 d2 d3 4 d124 d125 d126 d127 d0 d1 d2 d3 d4 5 d125 d126 d127 d0 d1 d2 d3 d12 d5 6d126d127 1 ws d0 d1 d2 d3 d12 d5 7d127 1 ws 1 ws d0 d1 d2 d3 d12 d5 january 28, 2008 s29ws-p_00_a12 s29ws-p 25 data sheet 7.4.3 latency at end of word line for boundary crossi ng after seco nd read in continuous burst operation the following tables show the latency for boundary crossing after second read in a continuous burst operation. table 7.20 address latency for 3 wait states word initial wait 0 3 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d121 d122 d123 d124 d125 d126 d127 d0 d1 2 d122 d123 d124 d125 d126 d127 d0 d1 d2 3 d123 d124 d125 d126 d127 d0 d1 d2 d3 4 d124 d125 d126 d127 d0 d1 d2 d3 d4 5 d125 d126 d127 d0 d1 d2 d3 d4 d5 6 d126 d127 d0 d1 d2 d3 d4 d5 d6 7 d127 1 ws d0 d1 d2 d3 d4 d5 d6 table 7.21 address latency for 11 wait states word initial wait 0 11 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 1 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 2 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 3 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 4 d116 d117 d118 d119 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 5 d117 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 6 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 7 d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 2 ws d0 table 7.22 address latency for 10 wait states word initial wait 0 10 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 1 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 2 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 3 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 4 d116 d117 d118 d119 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 5 d117 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 6 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 7 d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 1 ws d0 table 7.23 address latency for 9 wait states word initial wait 0 9 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d116 d117 d118 d119 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d117 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 7d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 26 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table 7.24 address latency for 8 wait states word initial wait 0 8 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d116 d117 d118 d119 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d117 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 7 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 table 7.25 address latency for 7 wait states word initial wait 0 7 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d116 d117 d118 d119 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 7 d117 d118 d119 1 ws 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 table 7.26 address latency for 6 wait states word initial wait 0 6 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 7 d116 d117 d118 d119 1 ws 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 table 7.27 address latency for 5 wait states word initial wait 0 5 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 7 d115 d116 d117 d118 d119 1 ws 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 january 28, 2008 s29ws-p_00_a12 s29ws-p 27 data sheet table 7.28 address latency for 4 wait states word initial wait 0 4 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 7 d114 d115 d116 d117 d118 d119 1 ws 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 table 7.29 address latency for 3 wait states word initial wait 0 4 ws d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 1 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 2 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 3 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 4 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 5 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 6 d112 d113 d114 d115 d116 d117 d118 d119 d120 d121 d122 d123 d124 d125 d126 d127 d0 7 d113 d114 d115 d116 d117 d118 d119 1 ws d120 d121 d122 d123 d124 d125 d126 d127 d0 28 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 7.5 synchronous (burst) read mode & configuration register see configuration registers on page 31 , and table 12.1, memory array commands on page 84 , for further details. figure 7.1 synchronous/asynchronous state diagram power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1) january 28, 2008 s29ws-p_00_a12 s29ws-p 29 data sheet figure 7.2 synchronous read flow chart 7.5.1 continuous burst read mode in the continuous burst read mode, the device output s sequential burst data from the starting address given and then wraps around to address 000000h when it reac hes the highest addressable memory location. the burst read mode continues until the system drives ce# high, or reset#= v il . continuous burst mode can also be aborted by asserting avd# low and providing a new address to the device. if the address being read crosses a 128-word line boundar y with in the same bank, but not into a program or erase suspended sector (as mention ed above), additional latency cycles are required as re flected by the configuration register table ( table 7.31 ). if the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and avd# pulse. write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait t iacc + programmable wait state setting wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 cr13-cr11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles note: setup configuration register parameters refer to the latency tables. 30 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 7.5.2 8-, 16-, 32-word linear burst read with wrap around in a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within wh ich the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see table 7.30 ). for example, if the starting address in the 8-word mode is 3ch, the address range to be read would be 38- 3fh, and the burst sequence would be 3c-3d-3e-3f-38-39-3a-3bh. thus , the device outputs all words in that burst address group until all word ar e read, regardless of where the starting address occurs in the address group, and then terminates the burst read. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. note in this mode the address pointer does not cross t he boundary that occurs every 128 words; thus, no additional wait states are in serted due to boundary crossing. 7.5.3 8-, 16-, 32-word linear burst without wrap around if wrap around is not enabled for linear burst read operat ions, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected num ber of words. the burst stops after 8, 16, or 32 addresses and does not wrap around to t he first address of the selected group. for example, if the starting address in the 8-word mode is 3ch, the address range to be read would be 3ch- 43h, and the burst sequence would be 3c-3d-3e-3f-40-41 -42-43h if wrap around is not enabled. the next address to be read requires a new address and avd# pulse. note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state. table 7.30 burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,... january 28, 2008 s29ws-p_00_a12 s29ws-p 31 data sheet 7.5.4 configuration registers this device uses two 16-bit config uration registers to set various operational parameters. upon power-up or hardware reset, the device defaults to the asynchronou s read mode, and the configuration register settings are in their default st ate. the host system should determine the proper settings for the entire configuration register, and then execute the set configuration re gister command sequence before attempting burst operations. the configuration register can also be read using a command sequence (see table 12.1 on page 84 ). the following list describes the register settings. notes: 1. device will be in the asynchronous mode upon power-up or hardware reset. 2. cr1.0 to cr1.3 and cr1.5 to cr1.15 = 1 (default). 3. cr0.3 is ignored if in continuous read mode (no warp around). 4. a software reset command is required after reading or writing the configuration registers in order to set the device back to array read mode. table 7.31 configuration register cr bit function settings (binary) cr0.15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) cr0.14 reserved (not used) 0 = reserved 1 = reserved (default) cr1.0 programmable wait state 0000 = initial data is valid on the 2nd rising clk edge after addresses are latched 0001 = initial data is valid on the 3rd rising clk edge after addresses are latched 0010 = initial data is valid on the 4th rising clk edge after addresses are latched 0011 = initial data is valid on the 5th rising clk edge after addresses are latched 0100 = initial data is valid on the 6th rising clk edge after addresses are latched 0101 = initial data is valid on the 7th rising clk edge after addresses are latched 0110 = reserved 0111 = reserved 1000 = initial data is valid on the 8th rising clk edge after addresses are latched 1001 = initial data is valid on the 9th rising clk edge after addresses are latched 1010 = initial data is valid on the 10th rising clk edge after addresses are latched 1011 = initial data is valid on the 11th rising clk edge after addresses are latched 1100 = reserved 1101 = default 1110 = reserved 1111 = reserved cr0.13 cr0.12 cr0.11 cr0.10 rdy polarity 0 = rdy signal is active low 1 = rdy signal is active high (default) cr0.9 reserved (not used) 0 = reserved 1 = reserved (default) cr0.8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) cr0.7 reserved (not used) 0 = reserved 1 = reserved (default) cr0.6 reserved 0 = reserved 1 = reserved (default) cr0.5 reserved 0 = reserved (default) 1 = reserved cr0.4 rdy function 0 = rdy (default) 1 = reserved cr0.3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr0.2 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) cr0.1 cr0.0 32 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 5. refer to table 12.1 on page 84 for reading the settings and writing ont o configuration registers command sequences. 6. configuration registers can not be programmed out of order. cr0 must be programmed prior to cr01 otherwise the configuration registers will retain their previous settings. 7.6 autoselect the autoselect is used for manufactur er id, device identification, and sector protection information. this mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. the autoselect codes can al so be accessed in-system. when verifying sector protection, the sector address must appear on t he appropriate highest order address bits (see table 7.32 on page 32 ). the remaining address bits are don't care. the mo st significant four bits of the address during the third write cycle selects the bank from which the autoselect codes are read by the host. all other banks can be accessed normally for data read without exiting the autoselect mode. ? to access the autoselect codes, the host system must issue the autoselect command. ? the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. autoselect does not support simultaneous operations or burst mode. ? the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). see table 12.1 on page 84 for command sequence details. table 7.32 autoselect addresses description address read data manufacturer id word 00 (ba) + 00h 0001h device id, word 01 (ba) + 01h 227eh sector lock/unlock word 02 (sa) + 02h 0001h = locked, 0000h = unlocked indicator bits word 03 (ba) + 03h dq15 - dq8 = reserved dq7 - factory lock bit; 1 = locked, 0 = not locked dq6 -customer lock bit; 1 = locked, 0 = not locked dq5 - handshake bit; 1 = reserved, 0 = standard handshake dq4 & dq3 - wp# protection boot code; 00 = wp# protects both top boot and bottom boot sectors, dq2 - dq0 = reserved device id, word 0e (ba) + 0eh 223dh (ws512p)-1ce# 2242h (ws256p) 2244h (ws128p) device id, word 0f (ba) + 0fh 2200h january 28, 2008 s29ws-p_00_a12 s29ws-p 33 data sheet software functions and sample code notes: 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manufacturer id. refer to the spansion low level driver user?s guide for general information on spansion flash memory software development guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef volatile unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ table 7.33 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write ba+aaah ba+555h 0x00aah unlock cycle 2 write ba+555h ba+2aah 0x0055h autoselect command write ba+aaah ba+555h 0x0090h table 7.34 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write xxxxh xxxxh 0x00f0h 34 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 7.7 program/erase operations these devices are capable of several modes of progra mming and or erase operations which are described in detail in the following sections. however, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the configuration register ( table 7.31 on page 31 ). during synchronous write operations, including writ ing command sequences, the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. a ddresses are latched on the rising edge of avd# pulse or rising edge of clk or falling edge of we#, whichever occurs first. during asynchronous write operations, addresses are la tched on the rising edge of avd# or falling edge of we# while data is latched on the 1st rising edge of we#, or ce# whichever comes first. note the following: ? when the embedded program/erase algorithm is complete, the device returns to the read mode. ? the system can determine the status of the program/erase operation. refer to write operation status on page 47 for further information. ? while 1 can be programmed to 0 , a 0 cannot be programmed to a 1 . any such attempt will be ignored as only an erase operation can covert a 0 to a 1 . for example: old data = 0011 new data = 0101 result = 0001 ? any commands written to the device during the embedded program/erase algorithm are ignored except the program/erase suspend commands. ? secured silicon sector, autoselect, and cfi functions are unavailable when a program/erase operation is in progress. ? a hardware reset and/or power removal immediately terminates the program/erase operation and the program/erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries only for single word programming operation. see write buffer programming on page 36 when using the write buffer. january 28, 2008 s29ws-p_00_a12 s29ws-p 35 data sheet 7.7.1 single word programming single word programming mode is the simplest met hod of programming. in this mode, four flash command write cycles are used to program an individual flash ad dress. while the single wo rd programming method is supported by all spansion devices, in general it is not recommended for devices that support write buffer programming. see table 12.1 on page 84 for the required bus cycles and figure 7.3 for the flowchart. when the embedded program algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. figure 7.3 single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa , p d unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) operation failed perform polling algorithm (see write operation status flowchart) ye s ye s no no polling status = busy? polling status = completed error condition (exceeded timing limits) operation successfully completed 36 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet software functions and sample code note: base = base address. the following is a c source code example of using the single word program function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 7.7.2 write buffer programming write buffer programming allows the system to write a maximum of 32 wo rds in one programming operation. this results in a faster effective wo rd programming time than the standard word programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer lo ad command written at the sector address in which programming will occur. at this point , the system writes the number of word locations minus 1 that will be loaded into the page buffer at the sector address in which programming will occur. this tells the device how many write buffer addresses will be loaded wit h data and therefore when to expect the program buffer to flash confirm command. the number of locations to progra m cannot exceed the size of the write buffer or the operation will abort. (note: the size of the write bu ffer is dependent upon which data are being loaded. also note that the number loaded = the numb er of locations to program minus 1. for example, if the system will program 6 address locations, then 05 h should be written to the device.) the write-buffer addresses must be in the same sector for a ll address/data pairs loaded into the write buffer. it is to be noted that write buffer programming ca nnot be performed across multip le sectors. if the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the write to buffer command is executed. also, the st arting address must be the le ast significant address. all subsequent addresses and write buffer data must be in sequential order. the system then writes the starting address/data combination. this starti ng address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must be in sequential order. after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. write buffer locations must be loaded in sequential order starting with the lowest address in the page. note that if the number of a ddress/data pairs do no match the word count, the program buffer to flash command is ignored. note that if a write buffer address lo cation is loaded multiple times, the address/data pair counter will be decremented for every data load operation. also , the last data loaded at a location before the program buffer to flash confirm command will be programmed into the dev ice. it is the software?s responsibility to comprehend ramifications of loading a write-buffer loca tion more than once. the counter decrements for each data load operation, not for each un ique write-buffer-address location. once the specified number of writ e buffer locations have been load ed, the system must then write the program buffer to flash command at the sector address. any ot her address/data write combinations will abort the write buffer programming operation. the device will then go busy . the data bar polling techniques table 7.35 single word program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word january 28, 2008 s29ws-p_00_a12 s29ws-p 37 data sheet should be used while monitoring the last address locati on loaded into the write buffer. this eliminates the need to store an address in memory because the syst em can load the last address location, issue the program confirm command at the last loaded address locati on, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitor ed to determine the device st atus during write buffer programming. the write-buffer embedded programming operation can be suspende d using the standard suspend/resume commands. upon successful completion of the write buffer programming operation, the device will return to read mode. the write buffer programming sequence is aborted in the following ways: ? load a value that is greater than the buffer size during the number of locations to program step (dq7 is not valid in this condition). ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different writ e-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. software functions and sample code notes: 1. base = base address. 2. last = last cycle of write buffer program operation; depend ing on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible . table 7.36 write buffer program (lld functions used = lld_writetobuf fercmd, lld_programbuffertoflashcmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h 38 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet the following is a c source code example of using the write buffer program function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* a write buffer begins at addresses evenly divisible */ /* by 0x20. uint16 i; */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)dst ) = 0x0025; /* write write buffer load command */ *( (uint16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i<=wc;i++) { *dst++ = *src++; /* all dst must be in same write buffer */ } *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ january 28, 2008 s29ws-p_00_a12 s29ws-p 39 data sheet figure 7.4 write buffer programming operation 7.7.3 program suspend/p rogram resume commands the program suspend command allows the system to interrupt an embedded programming operation or a write to buffer programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a progra mming process, the device halts the programming operation within t psl (program suspend latency). bank addr ess needs to be provided when writing the program suspend command. the status bits are undefined during the t psl period. to verify that the device is in the suspended state, either: ? wait until after t psl to check the status bits ? perform a read and check that the status bits return array data ? check whether any autoselect commands are accepted. after the programming operation has been suspended, the system can read array data from any non- suspended sector. the program suspend command may also be issued during a programming operation write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: program address data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 ye s ye s ye s ye s no no no no wc = 0? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. pass. device is in read mode. confirm command: 29h perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command 40 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then us er must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the auto select mode, the device reverts to program suspend mode, and is ready for another valid operation. see autoselect on page 32 for more information. after the program resume command is written, th e device reverts to prog ramming. the system can determine the status of the program operation using the dq7 or dq6 stat us bits, just as in the standard program operation. see write operation status on page 47 for more information. note: while a program operation can be suspended and resumed multiple times, a minimum delay of t prs (program resume to suspend) is requir ed from resume to the next suspend. the system must write the program resume command (address bits are don't care ) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. software functions and sample code the following is a c source code example of usin g the program suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of usi ng the program resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 7.7.4 sector erase the sector erase function erases one or more sectors in the memory array (see table 12.1 on page 84 and figure 7.5 on page 42 ). the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies th e entire memory for an all zero data pattern prior to electrical erase. after a successful sector erase, a ll locations within the erased sector contain ffffh. the system is not required to provide any cont rols or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. during the time- out period, additional sector addresse s and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of se ctors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets th at bank to the read mode. t he system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sector erase timeout state indicator on page 50 ). the time-out begins from the rising edge of the final we# pulse in the command sequence. table 7.37 program suspend (lld function = lld_programsuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h table 7.38 program resume (lld function = lld_programresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h january 28, 2008 s29ws-p_00_a12 s29ws-p 41 data sheet when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine t he status of the erase ope ration by reading dq7 or dq6/dq2 in the erasing bank. refer to write operation status on page 47 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset imme diately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 7.5 on page 42 illustrates the algorithm for the erase operation. refer to program/erase operations on page 34 for parameters and timing diagrams. software functions and sample code the following is a c source code example of us ing the sector erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ table 7.39 sector erase (lld function = lld_sectorerasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 sector erase command write sector address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within t sea . 42 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 7.5 sector erase operation notes: 1. see table 12.1 on page 84 for erase command sequence. 2. see the section on dq3 for information on the sector erase timeout. no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data january 28, 2008 s29ws-p_00_a12 s29ws-p 43 data sheet 7.7.5 chip erase command sequence chip erase is a six-bus cycle operation as indicated by table 12.1 on page 84 . these commands invoke the embedded erase algorithm, which does not require the system to preprog ram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all lo cations of the chip contain ffffh. the system is not required to provide any controls or timings during these operations. table 12.1 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system ca n determine the status of the erase operation by usi ng dq7 or dq6/dq2. refer to write operation status on page 47 for information on these status bits. any commands written during the chip erase operati on are ignored. however, note that a hardware reset immediately terminates the erase operation. if that o ccurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. software functions and sample code the following is a c source code example of us ing the chip erase function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ table 7.40 chip erase (lld function = lld_chiperasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h 44 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 7.7.6 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during th e sector erase operati on, after the minimum t sea time-out period during the sector er ase command sequence. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is written after the t sea time-out period has expired and during the sector erase operation, the device requires a minimum of t esl (erase suspend latency) to suspend the erase operation. the status bits are undefined during the t esl period. to verify that the device is in the suspended state, either: ? wait until after t esl to check the status bits ? perform a read and check that the status bits return array data ? check whether any autoselect commands are accepted after the erase operation has been suspended, the ba nk enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any addre ss within erase-suspended se ctors produces status information on dq7-dq0. th e system can use dq7, or dq6, and dq2 t ogether, to determine if a sector is actively erasing or is erase-suspended. refer to table 7.47 on page 51 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq 7 or dq6 status bits, just as in the standard program operation. note: while an erase operation can be suspended and resumed multiple times, a minimum delay of t ers (erase resume to suspend) is required from resume to the next suspend. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to write buffer programming on page 36 and autoselect on page 32 for details. to resume the sector erase operation, the syst em must write the erase resume command. the bank address of the erase-suspended bank is required when wr iting this command. furthe r writes of the resume command are ignored. another erase su spend command can be written afte r the chip has resumed erasing. software functions and sample code the following is a c source code example of us ing the erase suspend function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of us ing the erase resume function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for gen eral information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ table 7.41 erase suspend (lld function = lld_erasesuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h table 7.42 erase resume (lld function = lld_eraseresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h january 28, 2008 s29ws-p_00_a12 s29ws-p 45 data sheet 7.7.7 accelerated program/erase accelerated single word pr ogramming, write buffer programming, sector erase, and chip erase operations are enabled through the acc function. this method is fa ster than the standard chip program and erase command sequences. the accelerated program and erase functions must not be used mo re than 10 times per sector. in addition, accelerated program and erase shou ld be performed at room temperature (25 c 10 c). if the system asserts v hh on this input, the device automatically enters the accelerated mode and uses the higher voltage on the input to reduce the time requi red for program and erase operations. the system can then use the write buffer load command sequence prov ided by the unlock bypass mode. note that if a write-to-buffer-abort reset is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising acc to v hh . ? the acc pin must not be at v hh for operations other than accelerated programming accelerated erase, or device damage may result. ? the acc pin must not be left floating or unconnected ; inconsistent behavior of the device may result. ? acc locks all sector if set to v il ; acc should be set to v ih for all other conditions. 7.7.8 unlock bypass the unlock bypass feature allows t he system to primarily program fast er than using the standard program command sequence, and it is not intended for use du ring erase. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third wr ite cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the seco nd cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resu lting in faster total programming time. the erase command sequences are four cycles in length instead of six cycles. table 12.1 on page 84 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program, and unlock bypass reset commands are valid. to exit the unlock bypass mode , the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contai n the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the acc input. when the system asserts v hh on this input, the device automatically enters the unlock bypa ss mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to accelerate the operation. refer to erase/program timing on page 76 for parameters, and figure 11.15 on page 77 and figure 11.16 on page 77 for timing diagrams. 46 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet software functions and sample code the following are c source code examples of using t he unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; table 7.43 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h table 7.44 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation byte address word address data 1 program setup command write base + xxxh base +xxxh 00a0h 2 program command write program address program address program data table 7.45 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation byte address word address data 1 reset cycle 1 write base + xxxh base +xxxh 0090h 2 reset cycle 2 write base + xxxh base +xxxh 0000h january 28, 2008 s29ws-p_00_a12 s29ws-p 47 data sheet 7.7.9 write oper ation status the device provides several bits to determine the st atus of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the co mmand sequence. note that the data# polling is valid only for the last word being programmed in the write- buffer when write buffer programm ing is used. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. similarly, attempting to program 1 over a 0 does not return vali d date# information. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. the system must provide the program address to read valid status in formation on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately t psp , then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read m ode. if not all selected sectors are protected, the embedded eras e algorithm erases the unpr otected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address withi n a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6-dq1 while output enable (oe# ) is asserted low. that is, the device may change from providing status information to valid data on dq7. even if the de vice has completed the prog ram or erase operation and dq7 has valid data, the data output s on dq6-dq1 may be still invali d. valid data on dq7-dq1 appears on successive read cycles. see the following for more information: table 7.47 on page 51 , shows the outputs for data# polling on dq7. figure 7.6 on page 48 , shows the data# polling algorithm; and figure 11.19 on page 79 , shows the data# polling timing diagram. 48 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 7.6 write operation status flowchart notes: 1. dq6 is toggling if read2 dq6 does not equal read3 dq6. 2. dq2 is toggling if read2 dq2 does not equal read3 dq2. 3. may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4. write buffer error if dq1 of last read =1. 5. invalid state, use reset command to exit operation. 6. valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. data polling algorithm valid for all operations except advanced sector protection. start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5) january 28, 2008 s29ws-p_00_a12 s29ws-p 49 data sheet dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and du ring the sector erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately t asp [all sectors protected toggle time], then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protec ted sector, dq6 toggles for approximately t pa p after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 7.6 on page 48 , figure 11.20 on page 79 , and table 7.46 on page 49 and table 7.47 on page 51 . toggle bit i on dq6 requir es read address to be relatched by toggling avd# for each reading cycle. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to table 7.46 to compare outputs for dq2 and dq6. see the fo llowing for additional information: figure 7.6 on page 48 , dq6: toggle bit i on page 49 , and figures 11.19 ? 11.22 . read address has to be relatched by toggling avd# for each reading cycle. table 7.46 dq6 and dq2 indications if device is and the system reads then dq6 and dq2 programming, at any address at the bank being programmed toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address at the bank being programmed toggles, is not applicable. 50 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, th e system would note and store the value of the toggle bit after the first read. after the second read, th e system would compare the new value of the toggle bit with the first. if the toggle bit is no t toggling, the device has completed the program or erases operation. the system can read array data on dq7? dq0 on the follo wing read cycle. however, if after the in itial two read cycles, the system determines that the toggle bit is st ill toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stoppe d toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has succes sfully completed the program or er ases operation. if it is still toggling, the device did not complete the operati on successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. th e system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choo se to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to det ermine the status of the operation. refer to figure 7.6 on page 48 for more details. note: when verifying the status of a wr ite operation (embedded program/e rase) of a memory bank, dq6 and dq2 toggle between high and low states in a series of consecutive and contiguous status read cycles. in order for this toggling behavior to be properly observ ed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. if it is not possible to temporarily prevent reads to other memory banks, then it is recommended to use the dq7 status bit as the alternative method of determining the active or inactive status of the write operation. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that th e program or erase cycle was not successfully completed. the device does not output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1 , while any other bits that were correctly req uested to be changed from 1 to 0 are programmed. attempting to program a 0 to a 1 is masked during the programming operation. under valid dq5 conditions, the syste m must write the reset command to return to the read mode (or to the eras e-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator after writing a sector erase comm and sequence, the system may read dq 3 to determ ine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip eras e command.) if additional sectors are selected for erasure, the entire time-out also ap plies after each additional sector erase command. when the time-out period is comp lete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase command sequence for more details. after the sector erase command is wr itten, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command has been accepted, the system softwa re should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq 3 is high on the second status check, the last command might not have been accepted. table 7.47 on page 51 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort dq1 indicates whether a write to buffer operation wa s aborted. under these conditions dq1 produces a 1 . the system must issue the write to buffer abort rese t command sequence to return the device to reading array data. see write buffer program ming operation for more details. january 28, 2008 s29ws-p_00_a12 s29ws-p 51 data sheet notes: 1. dq5 switches to ?1? when an embedded program or embedded erase o peration has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer programming indicates the data-bar for dq7 data for the last loaded write-buffer address location . 7.8 simultaneous read/program or erase the simultaneous read/program or erase feature allo ws the host system to read data from one bank of memory while programming or erasing another bank of memory. an erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 11.25 on page 82 shows how read and write cycles ma y be initiated for simultaneous operation with zero latency. refer to dc characteristics on page 67 for read-while-program and read-while-erase current specification. 7.9 writing commands/command sequences when the device is configured for asynchronous read, only asynchronous write operations are allowed, and clk is ignored. when in the synchronous read mode c onfiguration, the device is able to perform both asynchronous and synchronous write operations. clk a nd avd# induced address latches are supported in the synchronous programming mode. during a synch ronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector, multiple sectors, or the entire device. table 6.2 on page 17 and table 6.3 on page 18 indicate the address space that each sector occupies. the device address space is divided into sixteen banks: banks 1 through 14 contain only 64 kword sectors, while banks 0 and 15 contain both 16 kword boot sectors in addition to 64 kword sectors. a bank address is the set of address bits required to uniq uely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in dc characteristics on page 67 represents the active current specification for the write mode. ac characteristics-synchronous and ac characteristics-asynchronous contain timing specification tables and timing diagrams for write operations. table 7.47 write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer (note 5) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1 52 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 7.10 handshaking the handshaking fe ature allows the host system to det ect when data is ready to be read by simply monitoring the rdy pin which is a dedicated output and is controlled by ce#. 7.11 hardware reset the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, resets the configuration register, and ig nores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be rein itiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry whic h enables the system to read the boot-up firmware from the flash memory upon a system reset. see figure 11.5 on page 69 and figure 11.14 on page 75 for timing diagrams. 7.12 software reset software reset is part of the command set (see table 12.1 on page 84 ) that also returns the device to array read mode and must be used for the following conditions: ? to exit autoselect mode ? when dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed ? exit sector lock/unlock operation. ? to return to erase-suspend-read mode if the device was previously in erase suspend mode. ? after any aborted operations ? exiting read configuration registration mode software functions and sample code note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to t he read and address bits are ignored. ? reset commands are ignored once erasure has begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is complete ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the thir d cycle). this resets the bank to which the system was writing to the read mode. table 7.48 reset (lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h january 28, 2008 s29ws-p_00_a12 s29ws-p 53 data sheet ? if the program command sequence is written to a bank t hat is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer programming oper ation, the system must write the ?write to buffer abort reset? command sequence to reset the devi ce to reading array da ta. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details]. 54 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 8. advanced sector protection/unprotection the advanced sector protec tion/unprotection feature disables or ena bles programming or erase operations in any or all sectors and can be implemented thr ough software and/or hardware methods, which are independent of each other. this sectio n describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 8.1 on page 54 . figure 8.1 advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 4 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 5, 6 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 7, 8, 9 7. 0 = sector protected, 1 = sector unprotected. 8. dyb bits are only effective for sectors that not protected via ppb locking mechanism. 9. volatile bits: defaults to unprotected after power up. 5. 0 = sector protected, 1 = sector unprotected. 6. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 4. n = highest address sector. january 28, 2008 s29ws-p_00_a12 s29ws-p 55 data sheet 8.1 advanced sector protection software examples table 8.1 contains all possibl e combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. 8.2 lock register the lock register consists of 4 bits. the secured silicon sector protection bit is dq 0, persistent protection mode lock bit is dq1, password protection mode lock bi t is dq2, persistent sector protection otp bit is dq3. if dq0 is ?0?, it means that the customer secured silicon area is lo cked and if dq0 is ?1?, it means that it is unlocked. when dq2 is set to ?1? and dq1 is set to ?0?, the device can only be used in the persistent protection mode. when the device is set to password prot ection mode, dq1 is required to be set to ?1? and dq2 is required to be set to ?0?. dq3 is programmed in the spansion factory. when the device is programmed to disable all ppb erase command, dq3 outputs a ?0?, wh en the lock register bits ar e read. similarly, if the device is programmed to enable all ppb erase command, dq3 outputs a ?1? when th e lock register bits are read. likewise the dq4 bit is also programmed in the spansion factory. dq4 is the bit which indicates whether volatile sector protection bit (dyb) is protected or not after boot-up. when the device is programmed to set all volatile sector protection bit protected after power-up, dq4 outputs a ?0? when the lock register bits are read. similarly, when the device is programmed to set all volatile sector protection bit un- protected after power-up, dq4 outputs a ?1?. each of these bits in the lo ck register are non-volatile. dq15- dq5 are reserved and will be 1?s. for programming lock register bits refer to table 12.2 on page 86 . notes: 1. if the password mode is chosen, the password must be programme d and verified before setting the corresponding lock register b it (dq2). failing to program and verifying the password prior to settin g lock register (dq2), causes all sectors to lock out. 2. it is recommended a sector protection method to be chosen by programming dq1 or dq2 prior to shipment. 3. after the lock register bits command set entry sequence is writ ten, reads and writes for bank 0 are disabled, while reads fro m other banks are allowed until exiting this mode. simultaneous operation is only valid as long as lock register program command is not executed. 4. if both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 5. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection scheme are allowed. similarly, if the persistent m ode lock bit is programmed, the password mode is permanently disab led. 6. during erase/program suspend, asp entry commands are not allowed. 7. data polling can be done immediately after the lock register programming command sequence (no delay required). note that stat us polling can be done only in bank 0 8. reads from other banks (simultaneous operation) are not allow ed during lock register programming. this restriction applies to both synchronous and asynchronous read operations. table 8.1 sector protection schemes unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected table 8.2 lock register dq15-5 dq4 dq3 dq2 dq1 dq0 1?s reserved (default = 1) ppb one time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit 56 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet after selecting a sector protection method, each sect or can operate in any of the following three states: 1. constantly locked. the selected sectors are protecte d and can not be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protect ed and can be altered via software commands. 3. unlocked. the sectors are unprotected and c an be erased and/or programmed. these states are controlled by the bit types described in sections 8.3 ? 8.6 . 8.3 persistent protection bits the persistent protection bits ar e unique and nonvolatile for each sector and have the same endurances as the flash memory. preprogramming and verification prio r to erasure are handled by the device, and therefore do not require system monitoring. notes: 1. each ppb is individually programm ed and all are eras ed in parallel. 2. while programming ppb for a sector, array data can not be read from any other banks. 3. entry command disables reads and writes for the bank selected. 4. reads within that bank return the ppb status for that sector. 5. reads from other banks are allowed while program/erase is not allowed. 6. all reads must be performed using the asynchronous mode. 7. the specific sector address (amax-a14) are writ ten at the same time as the program command. 8. if the ppb lock bit is set, the ppb program or erase command does not execute and times-out without programming or erasing the ppb. 9. there are no means for individually erasing a s pecific ppb and no specific sector address is required for this operation. 10. the ppb exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for bank 0 11. the programming state of the ppb for a given sect or can be verified by writing a ppb status read command to the device as described by the flow chart shown in figure 8.2 on page 57 . 12. during ppb program / erase data polling can be done synchronously. 13. if the user attempts to program or erase a pr otected sector, the device ignores the command and returns to read mode. january 28, 2008 s29ws-p_00_a12 s29ws-p 57 data sheet figure 8.2 ppb program/erase algorithm read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa0 dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail end exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s 58 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 8.4 dynamic protection bits dynamic protection bits are volatile and unique for eac h sector and can be individually modified. dybs only control the protection scheme fo r unprotected sectors that have their ppbs cleared (erased to 1 ). by issuing the dyb set or clear command sequences, the dybs are set (programmed to 0 ) or cleared (erased to 1 ), thus placing each sector in the prot ected or unprotected state respective ly. this feature allows software to easily protect sectors against inadvertent changes ye t does not prevent the easy removal of protection when changes are needed. notes 1. the dybs can be set (programmed to 0 ) or cleared (erased to 1 ) as often as needed. when the parts are firs t shipped, the ppbs ar e cleared (erased to 1 ). 2. the default state of dyb is u nprotected after power up and all sectors can be modified depending on the status of ppb bit for that sector, (erased to 1 ). then the sectors can be modified depending upon the ppb state of that sector (see table 8.1 on page 55 ). 3. it is possible to have sectors that are persistent ly locked with sectors that are left in the dynamic state. 4. the dyb set or clear commands for the dynamic se ctors signify protected or unprotected state of the sectors respectively. however, if there is a ne ed to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit onc e again locks the ppbs, a nd the device operates normally again. 5. data polling is not available for dyb program / erase. 6. dyb read data can be done synchronously. 7. if the user attempts to program or erase a pr otected sector, the device ignores the command and returns to read mode. 8.5 persistent protection bit lock bit the persistent protection bit lock bit is a global vo latile bit for all sectors. when set (programmed to 0 ), it locks all ppbs and when cleared (programmed to 1 ), allows the ppbs to be ch anged. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to 0 ) only after all ppbs are c onfigured to the desired settings. january 28, 2008 s29ws-p_00_a12 s29ws-p 59 data sheet 8.6 password protection method the password protection method allows an even higher leve l of security than the pers istent sector protection mode by requiring a 64 bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications. notes 1. if the password mode is chosen, the password must be programmed and verified before setting the corresponding lock register bit (dq2). failing to program and verifying the password prior to setting lock register (dq2), causes all sectors to lock out. 2. there is no special addressing order required for programming the password. once the password is written and verified, the password mode locking bit must be set in order to prevent access. 3. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0 . 4. the password is all 1 s when shipped from the factory. 5. all 64-bit password combinations are valid as a password. 6. there is no means to verify what the password is after it is set. 7. the password mode lock bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 8. the password mode lock bit is not erasable. 9. the lower two address bits (a1?a0) are valid dur ing the password read, password program, and password unlock. 10. the exact password must be entered in order for the unlocking function to occur. 11. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combin ations in an attempt to correctly match a password. 12. approximately 1 s is required for unlocking the devi ce after the valid 64-bit password is given to the device. 13. password verification is only allowed during the password programming operation. 14. all further commands to the password region are disabled and all operations are ignored. 15. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 16. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank 0. reads and writes for other banks excluding bank 0 are allowed. 17. if the user attempts to program or erase a pr otected sector, the device ignores the command and returns to read mode. 18. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the c ontents of the protected sector. 19. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device. 60 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 8.3 lock register program algorithm 8.7 hardware data protection methods the device offers two main types of data protec tion at the sector level via hardware control: ? when wp# is at v il , the four outermost sectors (including secured silicon area) are locked. ? when acc is at v il , all sectors (including secured silicon area) are locked. there are additional methods by which intended or acci dental erasure of any se ctors can be prevented via hardware means. the following subs ections describes these methods: write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array. january 28, 2008 s29ws-p_00_a12 s29ws-p 61 data sheet 8.7.1 wp# method the write protect feature provides a hardware method of protecting the four outermos t sectors. this function is provided by the wp# pin and overrides the previous ly discussed sector protection/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the outermost boot sectors, as well as secured silicon area. the oute rmost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp# pin, the device reverts to whet her the boot sectors we re last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or un connected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution 8.7.2 acc method this method is similar to above, except it pr otects all sectors. once acc input is set to v il , all program and erase functions are disabled and hence all sectors (i ncluding the secured sili con area) are protected. 8.7.3 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase ci rcuits are disabled, and the device resets to reading array data. subsequent wr ites are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . table 8.3 s29ws512p sector protection dual boot configuration bank 0 sa000-sa003 wp# protected bank 1-7 no sector wp# protection bank 8-14 no sector wp# protection bank 15 sa514-sa517 wp# protected table 8.4 s29ws256p sector protection dual boot configuration bank 0 sa000-sa003 wp# protected bank 1-7 no sector wp# protection bank 8-14 no sector wp# protection bank 15 sa258-sa261 wp# protected table 8.5 s29ws128p sector protection dual boot configuration bank 0 sa000-sa003 wp# protected bank 1-7 no sector wp# protection bank 8-14 no sector wp# protection bank 15 sa130-sa133 wp# protected 62 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 8.7.4 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 8.7.5 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device d oes not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. 9. power conservation modes 9.1 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics on page 67 represents the standby current specification 9.2 automatic sleep mode the automatic sleep mode minimizes flash device e nergy consumption only while in asynchronous main array read mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is indep endent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the automatic sleep mode is disabled. note that a new burst operation is required to provide new data. i cc6 in dc characteristics on page 67 represents the automatic sleep mode current specification. 9.3 hardware reset# input operation the reset# input provides a hardware method of re setting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates an y operation in progress, tristates all outputs, resets the configuration register, and ig nores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma chine to reading array data. the ope ration that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draw s cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitry and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 9.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. january 28, 2008 s29ws-p_00_a12 s29ws-p 63 data sheet 10. secured silicon sector flash memory region the secured silicon sector provides an extra flash memo ry region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 word s in length that consists of 128 words for factory data and 128 words for custome r-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the fact ory indicator bit, dq7, (a t autoselect address 03h) is used to indicate whether or not the factory secured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. please note the following general conditions: ? while secured silicon sector access is enabled, simultaneous operations are allowed except for bank 0. ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads can be performed in the asynchronous or synchronous mode. ? burst mode reads within secured silicon sector wrap from address ffh back to address 00h. ? reads outside of sector 0 return memory array data. ? continuous burst read past the maximum address is undefined. ? sector 0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device is executing an embedded program or embedded erase algorithm. 10.1 factory secured silicon sector the factory secured silicon sector is always protected when shipped fr om the factory and has the factory indicator bit (dq7) permanently set to a 1 . this prevents cloning of a fa ctory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre pr ogrammed with one of the following: ? a random, 8 word secure esn only within the factory secured silicon sector ? customer code within the customer secu red silicon sector through the spansion ? programming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code programmed th rough the spansion programming services. spansion programs the customer's code, with or without t he random esn. the devices are then shipped from the spansion factory with the factory secured silicon sector and customer secured s ilicon sector permanently locked. contact your local representative for details on using spansion programming services. table 10.1 secured silicon sector addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh 64 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 10.2 customer secured silicon sector the customer secured silicon sector is typically shipped unprotected (dq6 set to 0 ), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is pr otected, the customer indicator bit is permanently set to 1 . ? the customer secured silicon sector can be read any number of times, but can be programmed and locked only once. the customer secured silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the cust omer secured silicon sector area and none of the bits in the customer secured silicon sect or memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when programming the customer secured silicon sector, but reading in banks 1 through 15 is available. ? once the customer secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence which return the device to the memory array at sector 0. 10.3 secured silicon sector entry/exit command sequences the system can access the secured s ilicon sector region by issuing th e three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secu red silicon sector command sequence. see command definition table [secured silicon sector command table, appendix table 12.1 on page 84 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factor y secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues unt il the system issues the exit secured silicon sector command sequence, or until power is removed from the device. software functions and sample code the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user?s guide (available soon on www.spansion.com) for general information on spansion flash memory software development guidelines. note: base = base address. /* example: secured silicon sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secured silicon sector entry cmd */ table 10.2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h january 28, 2008 s29ws-p_00_a12 s29ws-p 65 data sheet note: base = base address. /* once in the secured silicon sector mode, you program */ /* words using the programming algorithm. */ note: base = base address. /* example: secured silicon sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secured silicon sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secured silicon sector exit cycle 4 */ table 10.3 secured silicon sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word table 10.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h exit cycle 3 write base + aaah base + 555h 0090h exit cycle 4 write any address any address 0000h 66 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 11. electrical specifications 11.1 absolute maximum ratings notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 11.2 . 2. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on pin acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 11.1 maximum negative overshoot waveform figure 11.2 maximum positive overshoot waveform 11.2 operating ranges note operating ranges define those limits between wh ich the functionality of the device is guaranteed. storage temperature plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) ?0.5 v to + 2.5 v v cc (note 1) ?0.5 v to +2.5 v acc (note 2) ?0.5 v to +9.5 v output short circuit current (note 3) 100 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v wireless (i) devices ambient temperature (t a ) ?25c to +85c supply voltages v cc supply voltages +1.70 v to +1.95 v january 28, 2008 s29ws-p_00_a12 s29ws-p 67 data sheet 11.3 dc characteristics 11.3.1 cmos compatible notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. i cc active while embedded erase or embedded program is in progress. 3. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 4. total current during accelerated programming is the sum of v acc and v cc currents. 5. v ccq = v cc during all i cc measurements. 6. v ih = v cc 68 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 11.4 test conditions figure 11.3 test setup 11.5 key to switching waveforms 11.6 switching waveforms figure 11.4 input waveforms and measurement levels table 11.2 test specifications test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 1.0 - 1.50 ns input pulse levels 0.0?v cc v input timing measurement reference levels v cc /2 v output timing measurement reference levels v cc /2 v c l device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) table 11.3 v cc power-up parameter description test setup time unit t vcs v cc setup time min 30 s t rh time between reset# (high) and ce# (low) min 200 ns v cc 0.0 v output measurement level input v cc /2 v cc /2 all inputs and outputs january 28, 2008 s29ws-p_00_a12 s29ws-p 69 data sheet 11.7 power-up/initialization power supply must reach its minimum voltage ran ge before applying/removing the next supply voltage. reset# must ramp down to v il level before v cc /v ccq can start ramp up. v cc and v ccq must be ramped simultaneously for proper power-up. the s29ws-p device ramp rate is > 1v/400 s. for v cc ramp rate <1v/400 s, a hardware reset is required. figure 11.5 v cc power-up diagram 11.8 clk characterization figure 11.6 clk characterization v cc / v ccq reset# t vcs t rh ce# v cc min v ih parameter description 54 mhz 66 mhz 80 mhz 104 mhz unit f clk clk frequency max546680 104 mhz min 60 khz in 8 word burst, 120 khz in 16 word burst, 250 khz in 32 word burst, 1 mhz in continuous mode t clk clk period min 18.5 15.1 12.5 9.62 ns t cl /t ch clk low/high time min 0.45 t clk ns max 0.55 t clk t cr clk rise time max 3.0 3.0 2.5 1.5 ns t cf clk fall time t clk t cl t ch t cr t cf clk 70 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 11.9 ac characteristics 11.9.1 synchronous/burst read notes: 1. addresses are latched on the rising edge of clk 2. synchronous access time is calculated using the formula (#of ws - 1)*(clock period) + (t bacc or clock to out) parameter description 54 mhz 66 mhz 80 mhz 104 mhz unit jedec standard t iacc synchronous access time max (ws-1) * t ck + t bacc ns t bacc burst access time valid clock to output delay max 13.5 11.2 9 7.6 ns t acs address setup time to clk (note 1) min 5 4 4 3.5 ns t ach address hold time from clk (note 1) min 6 6 5 5 ns t bdh data hold time min 4 3 3 2 ns t rdy chip enable to rdy active max 10 ns t oe output enable to rdy low max 13.5 11.2 9 7.6 ns t cez chip enable to high z max 10 10 10 7 ns t oez output enable to high z max 10 10 10 7 ns t ces ce# setup time to clk min 6 ns t racc ready access time from clk max 13.5 11.2 9 7.6 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk setup time min 6 ns t avd avd# pulse min t clk ns table 11.4 non-continuous burst mode with wrap around burst mode. max frequency wait state requirement frequency 27 mhz 3 27 mhz < frequency 40 mhz 4 40 mhz < frequency 54 mhz 5 54 mhz < frequency 66 mhz 6 66 mhz < frequency 80 mhz 7 80 mhz < frequency 95 mhz 8 95 mhz < frequency 104 mhz 11 table 11.5 continuous burst mode with no wrap around burst mode. max frequency wait state requirement frequency 27 mhz 3 27 mhz < frequency 40 mhz 4 40 mhz < frequency 54 mhz 6 54 mhz < frequency 66 mhz 7 67 mhz < frequency 80 mhz 8 80 mhz < frequency 95 mhz 9 95 mhz < frequency 104 mhz 11 january 28, 2008 s29ws-p_00_a12 s29ws-p 71 data sheet figure 11.7 8-word linear synchronous single data rate burst with wrap around notes: 1. figure shows for illustration the total nu mber of wait states set to seven cycles. 2. the device is configured synchronous single data rate mode and rdy active with data. 3. ce# (high) drives the rdy to hi-z while oe# (high) drives the dq(15:0) pins to hi-z. figure 11.8 8-word linear single data read synchronous burst without wrap around notes: 1. figure shows for illustration the total nu mber of wait states set to seven cycles. 2. the device is configured synchronous single data rate mode and rdy active with data. 3. ce# (high) drives the rdy to hi-z while oe# (high) drives the dq(15:0) pins to hi-z. dc dd oe# data address ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t bdh de db 7 cycles for initial access is shown as an illustration. hi-z t racc 1234567 t bacc t rdy t iacc t clkh t clkl t clk high-z t cez t oez t cez high-z dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df d13 7? cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t rdy d10 t racc 72 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 11.9.2 asynchronous mode read figure 11.9 asynchronous read mode (avd# toggling - case 1) notes: 1. valid address and avd# transition occur before ce# is driven low. 2. va = valid read address, rd = read data. parameter description asynchronous unit jedec standard t ce access time from ce# low max 83 ns t acc asynchronous access time max 80 ns t avdp avd# low time min 7.5 ns t aavds address setup time to rising edge of avd# min 6 ns t aavdh address hold time from rising edge of avd# min 4 ns t oe output enable to output valid max 13.5 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 4 ns t oez output enable to high z max 7.6 ns t cas ce# setup time to avd# min 0 ns t pa c c intra page access time max 20 ns t cez chip enable to high z max 7.6 ns clk v il or v ih ce# avd# oe# we# dq15-dq0 amax-a0 t oe va rd t ce t oez hi-z hi-z rdy t av d p t aavdh t cez t cez t rdy t wea t oeh t aavds january 28, 2008 s29ws-p_00_a12 s29ws-p 73 data sheet figure 11.10 asynchronous read mode (avd# toggling - case 2) notes: 1. avd# transition occurs after ce# is driven to low and valid address transition occurs before avd# is driven to low. 2. va = valid read address, rd = read data. figure 11.11 asynchronous read mode (avd# toggling - case 3) notes: 1. avd# transition occurs after ce# is driven to low and avd# is driven low before valid address transition. 2. va = valid read address, rd = read data. clk v il or v ih t oe va rd t oez ce# oe# we# amax-a0 avd# t av d p t aavdh dq15-dq0 t wea t cez hi-z hi-z rdy t cas t rdy t cez t oeh t aavds t acc clk v t oe va rd t oez ce# oe# we# amax-a0 avd# t av d p t aavdh dq15-dq0 t wea t cez hi-z hi-z rdy t cas t rdy t cez t oeh t aavds t acc il or v ih 74 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 11.12 asynchronous read mode (avd# tied to ce#) notes: 1. avd# is tied to ce# 2. va = valid read address, rd = read data. figure 11.13 asynchronous page mode read note ra = read address, rd = read data. clk v t rc ce# oe# we# dq15-dq0 amax-a0 t oe va rd t ce t oez t acc hi-z hi-z rdy t cez avd# t cez t rdy t oeh t wea il or v ih amax - a3 ce# oe# a2-a0 data bus page a0 a1 a2 ax d0 d1 dx d7 t acc t pac c t pac c t pac c avd# january 28, 2008 s29ws-p_00_a12 s29ws-p 75 data sheet 11.9.3 hardware reset (reset#) figure 11.14 reset timings table 11.6 hardware reset parameter description all speed options unit jedec std t rp reset# pulse width min 30 s t rh reset high time before read min 200 ns reset# t rp ce#, oe# t rh 76 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 11.9.4 erase/program timing notes 1. sampled, not 100% tested. 2. in programming operations, addresses are latched on the active edge of clk for programming synchronously or rising edge of av d# for programming asynchronously. 3. see the erase and programming performance on page 83 section for more information. does not include the preprogramming time. parameter description 54 mhz 66 mhz 80 mhz 104 mhz unit jedec standard t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time (note 2) synchronous min 5553.5 ns asynchronous 6666 t wlax t ah address hold time (note 2) synchronous min 7765 ns asynchronous 7765 t avdp avd# low time min 6 ns t dvwh t ds data setup time min 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t elwl t cs ce# setup time to we# min 4 ns t avsw avd# setup time to we# min 4 ns t avhw avd# hold time to we# min 4 ns t avsc avd# setup time to clk min5553ns t avhc avd# hold time to clk min5553ns t sea sector erase accept time-out min 50 s t esl erase suspend latency max 40 s t psl program suspend latency max 40 s t asp toggle time during erase within a protected sector typ 0 s t psp toggle time during programming within a protected sector typ 0 s january 28, 2008 s29ws-p_00_a12 s29ws-p 77 data sheet figure 11.15 asynchronous program operation timings notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. clk can be either v il or v ih . figure 11.16 synchronous program operation timings notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. addresses are latched on the first rising edge of clk. oe# ce# data addresses avd# we# clk t as t wp t ah t wc t wph pa t cs t dh t ch in progress va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h 555h pd t cas oe# ce# data addresses avd# we# clk 555h pd t wc t wph t wp pa t dh t ch in progress va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avhc t avsc t wc t avsw t avhw 78 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 11.17 chip/sector erase command sequence note: sa is the sector address for sector erase. figure 11.18 accelerated unlock bypass programming timing note: use setup and hold times from conventional program operation. oe# ce# data addresses avd# we# clk t as t wp t ah t wc t wph sa t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v hh 1 s v il or v ih t vids january 28, 2008 s29ws-p_00_a12 s29ws-p 79 data sheet figure 11.19 data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. figure 11.20 toggle bit timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data 80 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 11.21 synchronous data polling timings/toggle bit timings notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (d8 = 0 in the configuration register). when d8 = 1 in the configuration register, rdy is active one clock cycle before data. figure 11.22 dq2 vs. dq6 note: dq2 toggles only when read at an address within an erase-suspended se ctor. the system may use oe# or ce# to toggle dq2 and dq6. ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing january 28, 2008 s29ws-p_00_a12 s29ws-p 81 data sheet figure 11.23 latency with boundary crossing notes: 1. rdy active with data (cr0.8 = 0 in the configuration register). 2. rdy active one clock cycle before data (cr0.8 = 1 in the configuration register). 3. figure shows the device not crossing a bank in the process of performing an erase or program. figure 11.24 wait state configuration register setup clk address (hex) d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(note 1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(note 2) latency t racc t racc t racc t racc invalid data avd# oe# clk 1 2345 d0 d1 0 1 6 2 7 6 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data total number of clock edges following addresses being latched 48 10 12 14 13 82 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet figure 11.25 back-to-back read/write cycle timings note: breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. table 11.7 example of programmable wait states cr1.0 programmable wait state 0000 = initial data is valid on the 2rd rising clk edge after addresses are latched 0001 =initial data is valid on the 3rd rising clk edge after addresses are latched 0010 = initial data is valid on the 4th rising clk edge after addresses are latched 0011 = initial data is valid on the 5th rising clk edge after addresses are latched 0100 = initial data is valid on the 6th rising clk edge after addresses are latched 0101 = initial data is valid on the 7th rising clk edge after addresses are latched 0110 = reserved 0111 = reserved 1000 = initial data is valid on the 8th rising clk edge after addresses are latched 1001 = initial data is valid on the 9th rising clk edge after addresses are latched 101 1= initial data is valid on the 10th rising clk edge after addresses are latched . . 1101 = reserved 1110 = reserved 1111 = reserved cr0.13 cr0.12 cr0.11 oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph january 28, 2008 s29ws-p_00_a12 s29ws-p 83 data sheet 11.10 erase and programming performance notes: 1. typical program and erase values are measured at t c = 25c, 1.8 v v cc , 10,000 cycles using checkerboard patterns. sampled, but not 100% tested. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 4. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 12.1 on page 84 and table 12.2 on page 86 for further information on command definitions. 11.10.1 bga ball capacitance notes 1. sampled, not 100% tested. 2. test conditions t a - 25c; f = 1.0 mhz parameter typ (note 1) max (note 2) unit comments sector erase time 64 kword v cc 0.6 3.0 s excludes 00h programming prior to erasure (note 3) 16 kword v cc 0.35 1.75 chip erase time v cc 78.4 (ws128p) 155.2 (ws256p) 308.8 (ws512p) 154 (ws128p) 308 (ws256p) 616 (ws512p) s single word programming time v cc 40 400 s excludes system level overhead (note 4) acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 acc 192 1920 chip programming time (using 32 word buffer) v cc 50.4 (ws128p) 100.8 (ws256p) 201.6 (ws512p) 157.3 (ws128p) 314.6 (ws256p) 1008 (ws512p) s excludes system level overhead (note 4) acc 33.6 (ws128p) 67.2 (ws256p) 134.4 (ws512p) 100.7 (ws128p) 201.3 (ws256p) 402.6 (ws512p) erase suspend/erase resume (t ers )40 s program suspend/program resume (t prs ) 40 s parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 2 10 pf c out output capacitance v out = 0 2 10 pf 84 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 12. appendix this section contains information relating to softwar e control or interfacing with the flash device. for additional information and assistance regarding software, see additional resources on page 15 , or explore the web at www.spansion.com . legend x = don?t care ra = read address rd = read data pa = program address. addresses latch on the rising edge of th e avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edg e of we# or ce# pulse, whichever occurs first. notes 1. see table 7.1 on page 19 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: r ead cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15?dq8 are don?t care in command s equences, except for rd, pd, wd, pwd, and pwd3-pwd0. 5. unless otherwise noted, address bits amax?a14 are don?t cares. table 12.1 memory array commands command sequence (notes) cycles bus cycles ( note 1 - 6 ) first second third fourth fifth sixth addr data (19) addr data (19) addr data (19) addr data (19) addr data (19) addr data (19) asynchronous read (7) 1ra rd reset (8) 1 xxx f0 autoselect ( 9 ) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 0001 device id (10) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba)x 0e (10) (ba) x0f (10) indicator bits 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 (12) sector unlock/lock verify (11) 4 555 aa 2aa 55 (sa) 555 90 (sa) x02 0000/ 0001 single word 4 555 aa 2aa 55 555 a0 pa data write buffer to flash program (17) 6 555 aa 2aa 55 sa 25 sa wc pa (20) pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (12) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (15) 1ba b0 program/erase resume (16) 1ba 30 set configuration register (21) 5 555 aa 2aa 55 555 d0 x00 cr0 x01 cr1 read configuration register 4 555 aa 2aa 55 555 c6 x0 (0 or 1) cr (0 or 1) cfi query (17) 1 (ba) 55 98 unlock bypass mode unlock bypass entry (18) 3 555 aa 2aa 55 555 20 unlock bypass program ( 13 , 14 ) 2xx a0 pa pd unlock bypass sector erase ( 13 , 14 ) 2xx80sa30 unlock bypass erase ( 13 , 14 ) 2xx 80 xxx 10 unlock bypass cfi ( 13 , 14 )1 xx 98 unlock bypass reset 2 xx 90 xxx 00 january 28, 2008 s29ws-p_00_a12 s29ws-p 85 data sheet 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspe nd) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. the fourth cycle of the autoselect address is a r ead cycle. the system must provide the bank address. 10. (ba) + 0eh ----> for ws128 = 2244h, ws256 = 2242h, ws512 = 223dh. (ba) + 0fh ----> for ws064/128/256/512 = 2200h 11. the data is 0000h for an unlocked sector and 0001h for a locked sector 12. see table 7.32, autoselect addresses on page 32 . 13. the unlock bypass command sequence is required prior to this command sequence. 14. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the pr ogram/erase suspend command is valid only during a program/ erase operation, and requires the bank address. 16. the program/erase resume command is valid only during the program/erase suspend mode, and requires the bank address. 17. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the max imum number of cycles in the command sequence is 37. 18. write buffer programming can be initiated after unlock bypass entry. 19. data is always output at the rising edge of clock. 20. must be the lowest address. 21. configuration registers can not be programmed out of order. cr0 must be programmed prior to cr01 otherwise the configuration registers will retain their previous settings 86 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table 12.2 sector protection commands (sheet 1 of 2) command sequence (notes) cycles bus cycles ( note 1 - 6 ) first second third fourth fifth sixth seventh addr data (10) addr data( (10) addr data( (10) addr data( (10) addr data( (10) addr data( (10) addr data( (10) secured silicon sector entry (5) 3 555 aa 2aa 55 555 88 program 4 555 aa 2aa 55 555 a0 pa pd read 1 sa data exit (7) 4 555 aa 2aa 55 555 90 xx 00 lock register register command set entry (5) 3 555 aa 2aa 55 555 40 register bits program (6) 2 xx a0 00 data register bits read 1 00 data register command set exit (7) 2xx 90 xx 00 password protection command set entry 3 555 aa 2aa 55 555 60 program (9) 2xx a0 00/ 01/ 02/ 03 pwd 0/ 1/ 2/ 3/ read password (10) 400 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 unlock (9) 70025000300 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 protection command set exit 2xx 90 xx 00 ppb non-volatile sector protection command set entry (5) 3 555 aa 2aa 55 (ba) 555 c0 program 2 xx a0 (ba) sa 00 all erase (8) 2xx 80 xx 30 status read 1 (ba) sa rd(0) non-volatile sector protection command set exit (7) 2xx 90 xx 00 ppb lock bit global volatile sector protection freeze command set entry (5) 3 555 aa 2aa 55 555 50 set 2 xx a0 xx 00 status read 1 xx rd(0) global volatile sector protection freeze command set exit (7) 2xx 90 xx 00 dyb volatile sector protection command set entry (5) 3 555 aa 2aa 55 (ba) 555 e0 set 2 xx a0 (ba) sa 00 clear 2 xx a0 (ba) sa 01 status read 1 (ba) sa rd(0) volatile sector protection command set exit (7) 2xx 90 xx 00 january 28, 2008 s29ws-p_00_a12 s29ws-p 87 data sheet legend x = don?t care ra = read address rd = read data pa = program address. addresses latch on the rising edge of th e avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edg e of we# or ce# pulse, whichever occurs first. sa = sector address: ws128p = a22?a14, ws256p = 23?a14 ba = bank address: ws128p = a22-a20, and a19; ws256p = a23-a20 cr = configuration register data bits d15?d0 pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password. pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table 7.1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: r ead cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15?dq8 are don?t care in command s equences, except for rd, pd, wd, pwd, and pwd3-pwd0. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. if both the persistent protection mode locking bit and the pass word protection mode locking bit are set at the same time, the command operation aborts and returns the device to the default persistent sector protection mode during 2nd bus cycle. note that on all future devices, addr esses equal 00h, but is currently 77h for the ws512p only. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. ?all ppb erase? command pre-programs all ppbs before erasure to prevent over-erasure. 9. entire two bus-cycle sequence must be entered for each portion of the password. 10. full address range is required for reading password. accelerated program 2 555 a0 pa data sector erase 2 555 80 sa 30 chip erase 2 555 80 555 10 asynchronous read 1 ra rd write to buffer 4 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 table 12.2 sector protection commands (sheet 2 of 2) command sequence (notes) cycles bus cycles ( note 1 - 6 ) first second third fourth fifth sixth seventh addr data (10) addr data( (10) addr data( (10) addr data( (10) addr data( (10) addr data( (10) addr data( (10) 88 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 12.1 common flash memory interface the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-in dependent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device fam ilies. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address (ba)555h any time the device is ready to read arra y data. the system can read cfi information at the addresses given in tables 12.3?12.6 within that bank. all reads outside of the cfi address range, within the bank, returns non-valid data. reads from other banks ar e allowed, writes are not. to terminate reading cfi data, the system must wr ite the reset command. the following is a c source code example of using the cfi entry and exit f unctions. refer to the spansion low level driver user?s guide (available on www.spansion.com) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, pl ease refer to the cfi specification (s ee jedec publications jep137-a and jesd68.01). please contact your sales office for copies of these documents. table 12.3 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 12.4 system interface string addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0005h typical program time per single word write 2 n s (e.g. 30us) 20h 0009h typical program time using buffer 2 n s (e.g. 300us) (00h = not supported) 21h 000ah typical time for sector erase 2 n ms 22h 0000h typical time for full chip erase 2 n ms (00h = not supported) 23h 0003h max. program time per single word [2 n times typical value] 24h 0003h max. program time using buffer [2 n times typical value] 25h 0003h max. time for sector erase [2 n times typical value] 26h 0000h max. time for full chip erase [2 n times typical value] (00h = not supported) january 28, 2008 s29ws-p_00_a12 s29ws-p 89 data sheet table 12.5 device geometry definition addresses data description 27h 0018h (ws128p) 0019h (ws256p) 001ah (ws512p) device size = 2 n byte 28h 29h 0001h 0000h flash device interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte] [upper byte] (00h = not supported) 2ah 2bh 0006h 0000h max. number of bytes in multi-byte buffer write = 2 n [lower byte] [upper byte] (00h = not supported) 2ch 0003h number of erase block regions within device 01h = uniform sector; 02h = boot + uniform; 03h = boot + uniform + boot 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 1 information (small sector section) [lower byte] - number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors [upper byte] [lower byte] - equation =>(n = density in bytes of any 1 sector/256)h [upper byte] 31h 32h 33h 34h 007dh (ws128p) 00fdh (ws256p) 00fdh (ws512p) 0001h 0000h 0002h erase block region 2 information (large sector section) [lower byte] - number of sectors. [upper byte] [lower byte] - equation =>(n = density in bytes of any 1 sector/256)h [upper byte] 35h 36h 37h 38h 0003h 0000h 0080h 0000h erase block region 3 information (small sector section) [lower byte] - number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors [upper byte] [lower byte] - equation =>(n = density in bytes of any 1 sector/256)h [upper byte] 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information 90 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet table 12.6 primary vendor-specific exte nded query (sheet 1 of 2) addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major cfi version number, ascii 44h 0034h minor cfi version number, ascii 45h 0101b address sensitive unlock (bits 1-0) 00b = required, 01b = not required silicon technology (bits 5-2) 0011b = 130nm; 0100b = 110nm; 0101b = 90nm 001010b = 000ah 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protection per group 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08h = advanced sector protection; 07h = new sector protection scheme 4ah 07bh (ws128p) 0f3h (ws256p) 1e3h (ws512p) simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h write protect function 00h = no boot, 01h = dual boot, 02h = bottom boot, 03h = top boot 50h 0001h program suspend. 00h = not supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0008h secured silicon sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns (e.g. 10us => n=14) 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns (e.g. 10us => n=14) 55h 0005h erase suspend time-out maximum 2 n s 56h 0005h program suspend time-out maximum 2 n s 57h 0010h bank organization: x = number of banks 58h 0007h (ws064p) 000bh (ws128p) 0013h (ws256p) 0023h (ws512p) bank 0 region information. x = number of sectors in bank 59h 0004h (ws064p) 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 1 region information. x = number of sectors in bank 5ah 0004h (ws064p) 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 2 region information. x = number of sectors in bank 5bh 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 3 region information. x = number of sectors in bank january 28, 2008 s29ws-p_00_a12 s29ws-p 91 data sheet 5ch 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 4 region information. x = number of sectors in bank 5dh 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 5 region information. x = number of sectors in bank 5eh 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 6 region information. x = number of sectors in bank 5fh 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 7 region information. x = number of sectors in bank 60h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 8 region information. x = number of sectors in bank 61h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 9 region information. x = number of sectors in bank 62h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 10 region information. x = number of sectors in bank 63h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 11 region information. x = number of sectors in bank 64h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 12 region information. x = number of sectors in bank 65h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 13 region information. x = number of sectors in bank 66h 0008h (ws128p) 0010h (ws256p) 0020h (ws512p) bank 14 region information. x = number of sectors in bank 67h 000bh (ws128p) 0013h (ws256p) 0023h (ws512p) bank 15 region information. x = number of sectors in bank table 12.6 primary vendor-specific exte nded query (sheet 2 of 2) addresses data description 92 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet 13. revision history section description revision a6 (november 3, 2006) features removed zero hold mode switching waveforms revised v cc power-up diagram timing diagrams changed t cr to t rdy in figure 11.7 and figure 11.8 revision a7 (november 8, 2006) features updated effective write buffer programming per word erase/program timing t esl changed to max t psl changed to max cmos compatible removed note 2 from table. revision a8 (march 9, 2007) asynchronous mode read changed t cr to t rdy in figures 11.9 through 11.12 common flash memory interface revised device geometry table: ? changed ws512p data to 00fdh ? address 32h - data changed to 001h ? address 33h - data changed to 000h ? address 34h - data changed to 002h revised cfi table: removed uniform bottom, uniform top, and all sectors for address 4fh dc characteristics revised i ccb burst table revision a9 (march 28, 2007) dc characteristics revised i ccb for 108 mhz frequencies to tba synchronous/burst read revised t racc to 7.6 ns asynchronous mode read revised t aavdh to 4 ns revision a10 (april 20, 2007) ac characteristics removed wait state below 14 mhz, wait state 2 added additional wait state to all wait state frequency in table 11.4 added continuous burst mode synchro nous wait state requirement table revised burst access time to (ws-1) * t ck + (t bacc ) revision a11 (september 28, 2007) data sheet status changed to production global changed all 108 mhz to 104 mhz latency added 10 wait state and 11 wait state latency tables configuration registers added two more configur ations to cr0.11 for 10th and 11th rising clk edge ac characteristics revised t ces to 6 ns revised t avd to t clk dc characteristics changed description of i cc2 to v cc active program/erase current change descritpion of i cc5 to v cc active current (read while program/erase) erase/program timing and performance revised: t ers to 40 s t esl to 40 s t psl to 40 s t prs to 40 s output slew rate deleted programmable outuput slew rate control section revision a12 (january 28, 2008) configuration registers changed cr0.14 default setting to 1 january 28, 2008 s29ws-p_00_a12 s29ws-p 93 data sheet ac characteristics added device vcc ramp rate limit. updated timing diagrams for synchronous/burst read, asynchronous program operati on, synchronous program operation, and chip sector erase command sequence. program/erase operations added details to program and erase suspend/resume operations section description 94 s29ws-p s29ws-p_00_a12 january 28, 2008 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2006-2008 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries . other names used are for informational purposes only and may be trademarks of their respective owners. |
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